Introduction

    The world is seeing new technological advancements every day. With the advancing technology, the density of electronic devices is continuously increasing due to constantly reducing size. Some sub-micron devices included in a VLSI chip are bound to have some some imperfections. They result in yield-reducing manufacturing defects.  Therefore, there has come an increasing need for defect tolerance. Increasing attention is being paid to the development and use of defect-tolerance techniques for yield enhancement, to complement existing efforts at the manufacturing stage. 

    Defect Tolerance techniques are used to minimize the defect in the circuits and get the maximum possible yield from it. The motivation for incorporating defect tolerance is 2-fold: yield enhancement and reliability improvement. Both are achieved by restructuring the links so as to isolate the faulty elements. Restructuring capability is either static or dynamic in type. Which type is selected depends on whether restructuring should be performed only once after manufacturing, or an unlimited number of times, as may be required, throughout the operational life. The profitability of IC’s manufacturing depends heavily on the fabrication yield, defined as the proportion of operational circuits to the total number of fabricated circuits. A yield of 100% is unlikely, due to various manufacturing defects that exist even under mature manufacturing conditions. Continuous advances in manufacturing technologies have reduced the defect densities

    Manufacturing defects can be roughly classified into gross area defects and spot defects. Global defects are relatively large-scale defects, such as scratches from wafer mishandling, large-area defects from mask misalignment, and over- and under-etching. Spot defects are random local defects from materials used in the process and from environmental causes, mostly the result of undesired chemical and airborne particles deposited on the chip during the various steps of the process. Both types of defects contribute to the yield loss. Now in this survey we describe the nature of manufacturing defects and the way they affect the operation of a chip, and then show how to project the yield of a designed chip using statistical defect-distribution models. More important, we describe some defect-tolerance techniques for yield enhancement that can be employed during the design process, such as added redundancy and floorplan and layout modifications, and demonstrate their use in existing very large-scale-integration (VLSI) circuits.

    Over the course of time, in this blog, we will provide a detailed survey of Defect Tolerance and Yield enhancement techniques for VLSI circuits.



    Authors: Parth Pedgaonkar, Prabhanjan Pharkandekar, Celsy Phillips, Rushikesh Raje, Sakshi Raut.

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